PUMD13,135

Overview

The Nexperia PUMD13,135 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a SOT363-3 package. It features built-in bias resistors with R1 = 4.7 kΩ and R2 = 47 kΩ. The device supports a maximum collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is limited to 200 mW per transistor and 300 mW for the device at 25 °C ambient temperature. Transition frequencies are 230 MHz for the NPN section and 180 MHz for the PNP section.

Feature Summary

• Integrates NPN and PNP transistors with fixed internal bias resistors to reduce component count.
• Provides simplified circuit design by eliminating external base drive components.
• Offers low profile surface-mount packaging suitable for automated pick-and-place assembly.

Applications

• Low current peripheral driver circuits
• Control of IC inputs
• Replacement of general-purpose transistors in digital applications

Procurement Notes

Verify the specific ordering suffix matches the required reel quantity and manufacturing site code. Confirm that the SOT363-3 package variant aligns with the PCB footprint specifications used in the target design. Ensure compliance with RoHS and REACH regulations as stated in the product documentation before finalizing procurement orders.

Selection Notes

Select this component when a complementary NPN/PNP pair with integrated biasing is required. The fixed resistor values suit standard logic interface applications. Verify thermal constraints against the derating curve if operating above 25 °C. Consider the transition frequency limits for high-speed switching requirements compared to discrete alternatives.

Part Context

This part belongs to the PUMD13 family of resistor-equipped double transistors. Complementary configurations include the PUMB13 for PNP/PNP pairs and the PUMH13 for NPN/NPN pairs. All variants share similar electrical characteristics and package dimensions while differing in transistor polarity combinations.

Replacement Considerations

Direct substitutes include other RETs with identical pinouts and resistor ratios. Verify that alternative parts meet the 50 V breakdown and 100 mA current requirements. Check for equivalent transition frequencies and thermal resistance values to ensure performance parity in the existing circuit design.

FAQ

What are the specific values of the built-in bias resistors?

The input bias resistor R1 is 4.7 kΩ and the emitter bias resistor R2 is 47 kΩ.

What is the maximum total power dissipation for the device?

The total power dissipation is 200 mW per transistor and 300 mW for the entire device when mounted on an FR4 PCB at 25 °C ambient temperature.

Which package type does the PUMD13,135 utilize?

It utilizes the TSSOP6 plastic surface-mounted package, also known as SOT363-3 or SC-88.