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The Nexperia PUMD15 is a 50 V, 100 mA NPN/PNP resistor-equipped double transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mounted package. It integrates an NPN and a PNP transistor with built-in bias resistors R1 and R2, both nominally 4.7 kΩ. The device supports a maximum collector-emitter voltage of 50 V and a total power dissipation of 300 mW at 25 °C ambient temperature. It features a DC current gain (hFE) of at least 30 at 10 mA and includes AEC-Q101 qualification for automotive reliability.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the correct packaging format and manufacturing site code. Ensure that the selected variant matches the required tape and reel specifications for automated assembly processes. Cross-reference the marking code 'D0' followed by the site identifier to validate the physical component received against the purchase order.
Select this component when space constraints require a dual-transistor solution with integrated base biasing. The SOT363-3 package offers a compact footprint suitable for high-density PCB layouts. Verify that the 4.7 kΩ internal resistor values align with the target drive currents and logic levels of the controlling microcontroller or interface circuitry.
The PUMD15 belongs to the PUMD series of resistor-equipped double transistors from Nexperia. It serves as the NPN/PNP complement to the PUMH15 (NPN/NPN) and PUMB15 (PNP/PNP) variants. This family is designed to replace multiple discrete components in switching and driving applications, offering a standardized alternative to individual transistor and resistor combinations.
Direct functional replacements within the same package include the PUMD13 and PUMD14, which share the SOT363-3 form factor but may differ in internal resistor values or breakdown voltages. Verify pin compatibility and electrical parameters before substituting.