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The Nexperia PUMD16,115 is a dual Resistor-Equipped Transistor (RET) featuring an NPN and a PNP transistor within a TSSOP6 (SOT363-3) surface-mount package. It provides a collector-emitter voltage (VCEO) of 50 V and a continuous output current (IO) of 100 mA per transistor. The device integrates bias resistors with a nominal R1 value of 22 kΩ and an R2/R1 ratio of 2.1. Total power dissipation is rated at 200 mW per transistor and 300 mW for the complete device at 25 °C ambient temperature. The junction temperature maximum is 150 °C.
Verify the specific ordering suffix matches the required packaging format before procurement. Confirm that the TSSOP6 package version aligns with the target PCB footprint dimensions. Ensure thermal management strategies account for the specified junction-to-ambient resistance values under actual operating conditions.
Select this component when space constraints require a dual-transistor solution with integrated biasing. Compare the 22 kΩ input resistor value against logic gate output drive capabilities. Verify that the 50 V collector-emitter voltage rating exceeds the maximum expected signal swings in the application circuit.
This part belongs to the PUMD series of NPN/PNP resistor-equipped double transistors. Complementary configurations include the PUMH16 for NPN/NPN pairs and the PUMB16 for PNP/PNP pairs. All variants share the same SOT363-3 package outline and similar electrical characteristics tailored to their specific transistor polarities.
Direct functional substitutes include the PUMD13, PUMD14, and PUMD15 series from Nexperia, provided the internal resistor values match the circuit requirements. Other manufacturers' RETs in the SC-88 or SOT363 packages may be compatible if pinouts and electrical ratings are verified.