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The PUMD17,115 is an NPN/PNP resistor-equipped transistor array manufactured by Nexperia USA Inc. in a SOT363 (SC-88) surface-mount package. It integrates one NPN and one PNP transistor with built-in bias resistors: R1 = 47 kΩ and R2 = 22 kΩ. Key electrical parameters include a collector-emitter voltage of 50 V, DC output current of 100 mA, and total power dissipation of 300 mW at 25 °C ambient temperature. The device features a typical DC current gain of 60 at 5 mA and a saturation voltage of 150 mV at 10 mA.
Verify the specific ordering suffix to confirm the taping direction and reel specifications required for automated assembly. Confirm that the SOT363 package variant matches the footprint constraints of the target printed-circuit board design before finalizing procurement orders.
Select this component when a complementary NPN/PNP pair with fixed biasing is required. Ensure the 47 kΩ input resistance and 22 kΩ feedback resistance align with the driving source impedance and desired switching thresholds for the specific digital logic interface being implemented.
This part belongs to the PUMD series of resistor-equipped transistors designed for compact surface-mount applications. It serves as a direct replacement for discrete transistor networks, offering a standardized solution for signal conditioning and level shifting in consumer electronics and industrial control modules.
PEMD17 is available in the SOT666 package. PUMB17 and PEMH17 are alternative complements within the same family. Verify pinout compatibility and thermal characteristics when substituting these parts in existing designs.
The internal bias resistors are configured with R1 equal to 47 kΩ and R2 equal to 22 kΩ.
The maximum collector-emitter voltage (VCEO) is rated at 50 V for both the NPN and PNP transistors.
In the SOT363 package, the junction-to-ambient thermal resistance is 625 K/W per transistor and 416 K/W for the entire device at 25 °C ambient temperature.