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The Nexperia PUMD18 is a dual Resistor-Equipped Transistor (RET) featuring an NPN and a PNP transistor within a SOT363-3 (SC-88) surface-mounted package. It provides a maximum collector-emitter voltage of 50 V and an output current capability of 100 mA per transistor. The device integrates bias resistors with a nominal R1 value of 4.7 kΩ and an R2/R1 ratio of 2.1. Total power dissipation is rated at 300 mW, with a junction temperature limit of 150 °C. The component is qualified to the AEC-Q101 standard for automotive applications.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details such as reel or cut tape specifications. Ensure that the selected variant matches the required marking code and manufacturing site designation. Cross-reference the latest product data sheet to confirm availability status and any recent changes to the package type or qualification standards before finalizing procurement orders.
Select the PUMD18 when a complementary NPN/PNP pair with integrated biasing is required in a minimal footprint. The internal resistor values are fixed at 4.7 kΩ for R1 and approximately 10 kΩ for R2. This component replaces discrete transistor and resistor combinations, reducing PCB area. Verify that the 50 V voltage rating and 100 mA current limits meet the specific application requirements.
The PUMD18 belongs to Nexperia's family of double Resistor-Equipped Transistors designed for space-constrained designs. It serves as the NPN/PNP complement to the PUMH18 (NPN/NPN) and PUMB18 (PNP/PNP). The device utilizes the SOT363-3 package, which was updated from the previous SOT363 designation in recent revisions to reflect precise dimensional standards.
Direct functional equivalents include the PUMH18 for NPN/NPN configurations and the PUMB18 for PNP/PNP configurations. For single-transistor needs, consider discrete BJT alternatives or other RET variants with different resistor ratios. Verify pin compatibility and thermal characteristics when substituting.