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Product Detailed Parameters
- Description：TRANS PREBIAS 1NPN 1PNP 6TSSOP
- Series：-
- Mfr：Nexperia USA Inc.
- Package：Tape & Reel (TR)
- Transistor Type：1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max)：100mA
- Voltage - Collector Emitter Breakdown (Max)：50V
- Resistor - Base (R1)：22kOhms
- Resistor - Emitter Base (R2)：22kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce：60 @ 5mA, 5V
- pa_vce-saturation-max-ib-ic：
- Current - Collector Cutoff (Max)：100nA
- Frequency - Transition：230MHz, 180MHz
- Power - Max：300mW
- Grade：-
- Qualification：-
- Mounting Type：Surface Mount
- Package / Case：6-TSSOP, SC-88, SOT-363
- Supplier Device Package：6-TSSOP
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Overview
The PUMD2/DG/B3,115 is a dual pre-biased NPN/PNP transistor array manufactured by Nexperia USA Inc. It integrates one NPN and one PNP bipolar junction transistor within a single surface-mount package. The device features a maximum collector-emitter voltage of 50V and a continuous collector current of 100mA per transistor. Internal base resistors are specified at 22 kOhms for both the NPN and PNP sections. The component operates with a maximum power dissipation of 300mW and is housed in a compact 6-TSSOP (SC-88/SOT-363) footprint.
Feature Summary
- Integrates complementary NPN and PNP transistors with built-in biasing resistors to simplify circuit design.
- Provides high DC current gain characteristics suitable for switching applications.
- Features low saturation voltage to minimize power loss during conduction.
Applications
- General-purpose digital switching circuits
- Interface logic level translation
- Driver stages for small-signal loads
Procurement Notes
Verify the exact suffix against official Nexperia documentation to confirm resistor values and pinout compatibility. Ensure the ordering code matches the specific variant required for the design. Confirm RoHS compliance status through the manufacturer's latest release notes before finalizing procurement specifications.
Selection Notes
Select this component when a matched NPN/PNP pair with integrated biasing is required in a minimal footprint. Verify that the 22 kOhm internal resistance aligns with the target drive current and switching speed requirements. Ensure the 6-TSSOP package dimensions fit the available PCB space constraints.
Part Context
This part belongs to the PUMD2 family of dual pre-biased transistor arrays from Nexperia. These devices are designed to replace discrete resistor-transistor networks, reducing board space and assembly complexity. The DG/B3 suffix typically denotes specific manufacturing or packaging details within the broader product line.
Replacement Considerations
Publicly confirmed substitute part numbers are not available in the provided source material. Cross-referencing with other manufacturers requires careful verification of pinout, resistor values, and electrical ratings to ensure functional equivalence.
