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The PUMD2/DG/B3,135 is a dual pre-biased NPN transistor array manufactured by Nexperia USA Inc. It integrates two NPN transistors with individual base resistors in a compact surface-mount package. The device supports a maximum collector-emitter voltage of 50V and a continuous collector current of 100mA. Each transistor includes an internal base resistor (R1) of 47 kΩ. The component is rated for a maximum power dissipation of 300mW and operates within a junction temperature range up to 150°C. It is supplied in a 6-TSSOP (SC-88/SOT-363) package.
Verify the complete part number including the suffix /DG/B3,135 to ensure correct packaging and tape-and-reel specifications. Confirm RoHS compliance status and moisture sensitivity level requirements against specific manufacturing standards before procurement. Cross-reference the manufacturer's latest datasheet for any recent pinout or electrical parameter updates.
Select this component when a dual NPN solution with fixed base biasing is required to save board space. Ensure the 47 kΩ internal base resistance aligns with the driving source impedance and desired switching speed. Verify that the 100mA collector current rating meets the load requirements and that the 50V breakdown voltage exceeds the maximum operating voltage in the application circuit.
This component belongs to Nexperia's PUMD series of pre-biased resistor-equipped transistors. It serves as a complementary pair to the PUMH24 (NPN/NPN) and PUMB24 (PNP/PNP) variants, offering standardized integration for common emitter configurations. The series is designed to replace discrete transistor-resistor combinations in signal processing and switching roles.
Publicly confirmed substitute part numbers are not available in the provided documentation. Evaluate equivalent dual NPN pre-biased arrays from other manufacturers only if they match the 6-TSSOP footprint, 50V rating, 100mA current capacity, and 47 kΩ base resistance values.