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The PUMD20,115 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a SOT363-3 package. It features built-in bias resistors of 2.2 kΩ each (R1), with a typical R2/R1 ratio of 1. The collector-emitter voltage (VCEO) is 50 V per transistor, and the output current (IO) is 100 mA. Total power dissipation is 300 mW at Tamb ≤ 25 °C. Junction temperature ranges from -65 °C to +150 °C. Thermal resistance from junction to ambient is 416 K/W for the device.
Verify the specific ordering suffix matches the required packaging configuration before purchase. Confirm that the AEC-Q101 qualification aligns with target automotive reliability standards. Ensure thermal management strategies account for the specified total power dissipation limits under expected operating conditions.
Select this component when space constraints require a dual transistor solution with integrated biasing. The 50 V rating suits low-voltage logic interfacing. Verify input voltage limits (-12 V to +12 V) against the driving signal levels to prevent exceeding absolute maximum ratings during operation.
This part belongs to Nexperia's resistor-equipped transistor family. Complementary configurations include the PUMH20 (NPN/NPN) and PUMB20 (PNP/PNP). These devices replace discrete transistor-resistor networks to save board area and assembly time.
Direct functional substitutes within the same package include PUMH20 and PUMB20. Verify pin compatibility and electrical parameters match the original design requirements before substitution.
Both bias resistors R1 and R2 have a nominal value of 2.2 kΩ.
Yes, the PUMD20 is qualified according to the AEC-Q101 standard.
The input voltage range is -12 V to +12 V, depending on the specific transistor polarity.