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The PUMD2,115 is a dual pre-biased NPN/PNP transistor array manufactured by Nexperia USA Inc. It integrates one NPN and one PNP bipolar junction transistor within a single 6-TSSOP surface-mount package. The device supports a maximum collector-emitter voltage of 50V and a continuous collector current of 100mA. Internal base resistors are specified at 22 kΩ for both transistors. The unit delivers a minimum DC current gain of 60 at 5mA and 5V, with a maximum saturation voltage of 150mV under defined bias conditions. Thermal performance is rated at 300mW power dissipation, ensuring reliable operation in compact digital switching applications.
Verify the complete part number including the suffix against official Nexperia documentation to ensure correct packaging configuration. Confirm RoHS compliance status and specific reel quantities prior to ordering. Cross-reference the manufacturer part number with authorized distributor catalogs to validate authenticity and traceability. Ensure storage conditions align with moisture sensitivity levels defined in the datasheet.
Select this component when a matched NPN/PNP pair with integrated biasing is required for simplified circuit design. The fixed 22 kΩ internal resistors suit standard logic families operating at 5V. Evaluate thermal constraints based on the 300mW power rating and ambient temperature conditions. Consider the 6-TSSOP package dimensions for PCB layout compatibility compared to alternative transistor arrays.
This device belongs to the PUMD series of pre-biased BJT arrays from Nexperia. These components consolidate discrete transistor and resistor functions into a single package to minimize board space and assembly complexity. The PUMD2 variant specifically provides complementary polarity outputs, distinguishing it from single-type arrays like the PUMC or PUMT series.
Publicly confirmed substitute part numbers are not available in the provided source material.