PUMD24,115

Overview

The PUMD24,115 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a SOT363 (TSSOP6) package. It features built-in bias resistors R1 and R2, both nominally 100 kΩ. The device supports a maximum collector-emitter voltage of 50 V and an output current of 20 mA per transistor. Key electrical characteristics include a DC current gain (hFE) of at least 80 at 20 mA, a saturation voltage of 150 mV max, and a total power dissipation of 300 mW. It is qualified to AEC-Q101 standards for automotive applications.

Feature Summary

• Integrates NPN and PNP transistors with internal bias resistors to reduce component count
• AEC-Q101 qualified for automotive reliability requirements
• Compact SOT363 surface-mount package design

Applications

• Low current peripheral driver circuits
• Control of IC inputs
• Replacement of general-purpose transistors in digital logic applications

Procurement Notes

Verify the specific ordering suffix

Selection Notes

Select this component when space-constrained designs require paired NPN/PNP switching with fixed base drive. Ensure the 100 kΩ internal resistor values align with the target input logic levels and required drive currents. Verify that the 50 V voltage rating exceeds the maximum circuit operating voltage under all transient conditions.

Part Context

This part belongs to Nexperia's RET family, designed to simplify digital circuit layouts by combining transistors and biasing networks. Complementary variants include the PUMB24 (PNP/PNP) and PUMH24 (NPN/NPN). The SOT363 package allows for high-density PCB mounting compared to discrete transistor arrangements.

Replacement Considerations

Direct functional replacements within the same package and specification include PUMB24 for PNP/PNP configurations or PUMH24 for NPN/NPN pairs. Verify pinout compatibility and resistor tolerance specifications before substituting.