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The Nexperia PUMD30,115 is a 50 V, 100 mA NPN/PNP resistor-equipped double transistor (RET) housed in a SOT363 (SC-88) TSSOP6 plastic surface-mounted package. It integrates an NPN transistor with a 2.2 kΩ input bias resistor and a PNP transistor with an open emitter resistor. Key electrical parameters include a collector-emitter voltage of 50 V, output current capability of 100 mA per transistor, and total power dissipation of 300 mW at 25 °C ambient temperature. The device features a DC current gain (hFE) minimum of 30 at 20 mA and a collector-emitter saturation voltage maximum of 150 mV.
Verify the specific ordering suffix to confirm packaging configuration, as standard data sheets may not detail reel or cut tape variations. Confirm RoHS compliance status through official Nexperia channels prior to procurement. Ensure the selected variant matches the required marking code for manufacturing traceability. Cross-reference the latest datasheet revision to validate any recent changes to pinning or thermal characteristics before finalizing supply agreements.
Select this component when space-constrained designs require dual complementary transistors with integrated base biasing. The 2.2 kΩ internal resistor on the NPN side eliminates external components, reducing PCB area. Verify that the open emitter resistor configuration on the PNP side aligns with the target application's drive requirements. Consider the 300 mW total power dissipation limit when designing thermal management strategies for high-density layouts.
The PUMD30 belongs to Nexperia's PUMD series of resistor-equipped double transistors. It serves as the NPN/PNP complement to the PUMH30 (NPN/NPN) and PUMB30 (PNP/PNP). This family utilizes the compact SOT363 package to provide cost-effective solutions for signal switching and logic interface applications where minimal footprint and simplified biasing are critical design constraints.
Publicly confirmed substitute part numbers are not available in the provided documentation.