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The Nexperia PUMD3,125 is a dual digital transistor array housed in a SOT-363 (SC-88) surface-mount package. It integrates one NPN and one PNP bipolar junction transistor with built-in base resistors to simplify circuit design. The device supports a maximum collector current of 100 mA and offers a collector-emitter voltage rating of 50 V. Key electrical parameters include a minimum DC current gain (hFE) of 30, a maximum power dissipation of 300 mW, and a transition frequency of 180 MHz. The component operates within a temperature range of -65°C to +150°C.
Verify the specific suffix against official Nexperia documentation to confirm pinout compatibility and resistor values. Ensure the ordering code matches the required packaging format. Cross-reference the datasheet revision date to validate parameter accuracy before finalizing procurement specifications.
Select this component when space constraints require a compact dual-transistor solution with integrated biasing. Compare the internal resistor values against the target drive requirements to ensure adequate base current. Verify that the thermal dissipation limits align with the expected operating conditions of the application.
This part belongs to the Nexperia PUMD series of pre-biased digital transistors. These components are designed to replace discrete resistor and transistor combinations, reducing board space and assembly costs. The SOT-363 package is widely used in consumer electronics and mobile devices where miniaturization is critical.
Check for direct substitutes from other manufacturers offering identical pinouts and electrical characteristics. Verify that any alternative component meets the same AEC-Q101 qualification if automotive reliability is required.