PUMD3,135

PUMD3,135

$0.20
  • Description:TRANS PREBIAS 1NPN 1PNP 6TSSOP
  • Series:-

SKU:c74b4c9b454a Category: Brand:

  
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Product Detailed Parameters

  • Description:TRANS PREBIAS 1NPN 1PNP 6TSSOP
  • Series:-
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)
  • Transistor Type:1 NPN, 1 PNP - Pre-Biased (Dual)
  • Current - Collector (Ic) (Max):100mA
  • Voltage - Collector Emitter Breakdown (Max):50V
  • Resistor - Base (R1):10kOhms
  • Resistor - Emitter Base (R2):10kOhms
  • DC Current Gain (hFE) (Min) @ Ic, Vce:30 @ 5mA, 5V
  • pa_vce-saturation-max-ib-ic:
  • Current - Collector Cutoff (Max):1µA
  • Frequency - Transition:-
  • Power - Max:300mW
  • Grade:-
  • Qualification:-
  • Mounting Type:Surface Mount
  • Package / Case:6-TSSOP, SC-88, SOT-363
  • Supplier Device Package:6-TSSOP

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PUMD3,135

Overview

The Nexperia PUMD3,135 is a dual pre-biased NPN and PNP transistor array housed in a SOT-363 (SC-88) surface-mount package. It integrates internal base resistors to simplify circuit design. Key electrical parameters include a maximum collector-emitter voltage (Vceo) of 50 V, a maximum collector-base voltage (VCBO) of 50 V, and a continuous collector current (Idc) of 100 mA. The device features a minimum DC current gain (hFE) of 30, a maximum power dissipation (Pd) of 300 mW, and a transition frequency (ft) of 180 MHz. Operating temperatures range from -65°C to 150°C.

Feature Summary

  • Integrates NPN and PNP transistors with built-in base resistors for simplified biasing
  • Designed for high-frequency applications with specified transition frequency
  • Qualified for automotive electronics under AEC-Q101 standards

Applications

  • Automotive electronic systems requiring qualified discrete components
  • High-speed switching circuits utilizing integrated biasing
  • General-purpose digital logic interface buffering

Procurement Notes

Verify the specific suffix '135' against official Nexperia documentation to confirm reel packaging specifications. Ensure the selected variant matches the required SOT-363 footprint and pinout configuration for your PCB layout. Cross-reference datasheet revisions to confirm compliance with RoHS3 and REACH regulations before finalizing procurement orders.

Selection Notes

Select this component when a compact dual transistor solution with integrated biasing is required. Compare the 300 mW power dissipation limit against thermal constraints. Verify that the 180 MHz transition frequency meets signal speed requirements. Confirm compatibility with the target operating temperature range of -65°C to 150°C.

Part Context

This part belongs to the PUMD series of pre-biased resistor-equipped transistors. It serves as a space-saving alternative to discrete resistor-transistor combinations. The SOT-363 package provides a small form factor suitable for dense surface-mount assemblies. It complements other Nexperia BJT arrays like the PUMD10 and PUMD13.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided source material.

PUMD3,135PUMD3,135
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