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The Nexperia PUMD48 is a Resistor-Equipped Transistor (RET) double transistor featuring one NPN and one PNP unit in a TSSOP6 (SOT363-3) package. It provides a collector-emitter voltage of 50 V and an output current capability of 100 mA per transistor. The device integrates bias resistors: TR1 (NPN) includes R1 = 47 kΩ and R2 = 47 kΩ, while TR2 (PNP) includes R1 = 2.2 kΩ and R2 = 47 kΩ. Total power dissipation is rated at 300 mW at 25 °C ambient temperature.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact packaging configuration and manufacturing site code. Ensure that the selected variant matches the required tape and reel specifications for automated assembly processes.
Select this component when space constraints require a dual transistor solution with integrated base biasing. Verify that the internal resistor values align with the target logic levels and drive requirements for both NPN and PNP channels within the application circuit.
The PUMD48 belongs to Nexperia's family of Resistor-Equipped Transistors designed for compact digital logic interfaces. It consolidates discrete transistor and resistor functions into a single SMD footprint, facilitating miniaturization in portable electronics and dense printed circuit board layouts.
Consult official Nexperia cross-reference lists for verified substitutes. Ensure any replacement maintains identical pinout configurations, voltage ratings, and thermal characteristics to guarantee compatibility with existing PCB footprints.
For the NPN transistor (TR1), R1 is 47 kΩ and R2 is 47 kΩ. For the PNP transistor (TR2), R1 is 2.2 kΩ and R2 is 47 kΩ.
The total power dissipation (Ptot) is 300 mW when the ambient temperature is 25 °C or lower.
The device is housed in a TSSOP6 plastic surface-mounted package, also designated as SOT363-3.