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The PUMD48,165 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a TSSOP6 (SOT363-3) package. It supports a collector-emitter voltage of 50 V and an output current of 100 mA per transistor. The NPN section features a base bias resistor (R1) of 47 kΩ with a ratio of 1, while the PNP section has an R1 of 2.2 kΩ with a ratio of 21. Total power dissipation is 300 mW at 25 °C ambient temperature. The device operates within a junction temperature range of -65 °C to 150 °C.
Verify the specific ordering suffix against the manufacturer's latest documentation to ensure correct packaging configuration. Confirm that the requested quantity aligns with standard reel or cut tape specifications provided by authorized distributors. Cross-reference the date code and lot number to ensure compliance with current RoHS directives and material declarations before finalizing procurement orders.
Select this component when a complementary NPN/PNP pair with integrated biasing is required for digital logic interfacing. Ensure the application voltage does not exceed the 50 V collector-emitter rating. Verify that the internal resistor values match the drive requirements, noting the significant difference between the NPN input resistance and the lower PNP input resistance.
This part belongs to the Nexperia PUMD48 family of double resistor-equipped transistors. It serves as a complement to other RET variants such as the PUMH series for NPN/NPN configurations. The device is designed to simplify circuit layouts by replacing discrete transistor and resistor combinations in standard digital signal processing tasks.
Direct substitutes include other Nexperia RETs with similar pinouts and electrical characteristics, such as the PUMD19 or PRMD10, provided the internal resistor values meet the specific circuit design requirements. Verify package compatibility and thermal performance when swapping between different RET families.