PUMD6,125

Overview

The PUMD6,125 is a dual pre-biased NPN/PNP transistor array manufactured by Nexperia. It integrates one NPN and one PNP transistor within a single surface-mount package. The device features a maximum collector-emitter voltage (Vceo) of 50 V and a maximum DC collector current (Ic) of 100 mA. Internal base resistors are configured with R1 at 4.7 kΩ and R2 at 47 kΩ. The component operates within a temperature range of -55°C to +150°C and has a maximum power dissipation of 200 mW. It utilizes the US (SC-88/SOT-363) package type with six pins.

Feature Summary

• Integrates complementary NPN and PNP transistors in a compact footprint
• Includes internal base biasing resistors to simplify circuit design
• Supports high junction temperatures up to 150°C

Applications

• General-purpose switching applications
• Driver circuits for logic interfaces
• Signal level translation buffers

Procurement Notes

Verify the specific suffix against official Nexperia documentation to confirm pinout compatibility and resistor values. Ensure the selected variant matches the required thermal management specifications for the intended operating environment. Cross-reference datasheets for absolute maximum ratings before integration.

Selection Notes

Select this component when space-constrained designs require both NPN and PNP switching capabilities. Verify that the integrated resistor values align with the target drive currents. Confirm that the 50V breakdown voltage meets the system's peak voltage requirements under all load conditions.

Part Context

This part belongs to the PUMD series of pre-biased transistor arrays from Nexperia. These devices are designed to replace discrete resistor-transistor combinations, reducing board space and assembly complexity. The series offers various resistor configurations to suit different logic families and drive requirements.

Replacement Considerations

Direct substitutes include other Nexperia PUMD variants with matching resistor ratios. Third-party equivalents must be verified for identical pinouts, voltage ratings, and thermal characteristics to ensure functional parity.