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The Nexperia PUMD9,135 is a Resistor-Equipped double Transistor (RET) containing one NPN and one PNP transistor in a SOT363-3 package. It features built-in bias resistors with R1 = 10 kΩ and R2 = 47 kΩ. The device supports a collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is limited to 200 mW per transistor and 300 mW per device at 25 °C ambient temperature. Transition frequencies are 230 MHz for the NPN section and 180 MHz for the PNP section.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact tape and reel quantity or cut tape specifications. Confirm that the requested part number matches the required package version and manufacturing site code markings before finalizing procurement orders.
Select this component when a complementary NPN/PNP pair with integrated base biasing is required. Ensure the application voltage does not exceed 50 V and the continuous current remains within 100 mA limits. Verify thermal constraints if multiple units operate simultaneously on the same PCB footprint.
The PUMD9 belongs to the RET family designed to replace discrete resistor-transistor networks. It serves as a compact solution for digital switching tasks where space savings and reduced assembly costs are priorities. The device is functionally distinct from single-transistor variants like the PUMH9.
PUMD9,115
Pin 1 is GND1 (emitter), Pin 2 is I1 (base), Pin 3 is O2 (collector), Pin 4 is GND2 (emitter), Pin 5 is I2 (base), and Pin 6 is O1 (collector).
The typical value for bias resistor R1 is 10 kΩ, and the typical ratio for R2/R1 is 4.7.
Yes, it offers transition frequencies of 230 MHz for the NPN transistor and 180 MHz for the PNP transistor.