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The Nexperia PUMF11,115 is a dual transistor assembly in a SOT363 (SC-88) plastic surface-mount package. It integrates an NPN resistor-equipped transistor (TR1) and a general-purpose PNP transistor (TR2). The NPN device features built-in bias resistors R1 (22 kΩ) and R2 (47 kΩ), with a maximum collector-emitter voltage of 50 V and DC collector current of 100 mA. The PNP device supports a peak collector current of 200 mA and a collector-emitter voltage of -40 V. Total power dissipation is rated at 300 mW per device at 25 °C ambient temperature.
Verify the specific ordering suffix against official Nexperia documentation to confirm manufacturing origin details. Ensure compatibility with standard SOT363 footprints during layout. Confirm that thermal constraints align with the specified junction-to-ambient resistance values under actual operating conditions.
Select this component when space optimization is critical compared to using discrete SOT323 packages. Verify that the required logic levels match the input characteristics of the integrated NPN transistor. Consider the total power dissipation limits relative to the expected thermal environment of the final application.
This part belongs to the PUMF series of mixed transistor assemblies manufactured by Nexperia. It utilizes the SOT363 leadless surface-mount technology to provide high-density integration. The product line focuses on reducing pick-and-place costs and simplifying assembly processes for consumer electronics applications.
Direct replacement requires matching the SOT363 outline dimensions. Verify pinout compatibility, specifically the emitter, base, and collector assignments for both the NPN and PNP sections. Ensure electrical parameters meet or exceed the original requirements.