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The Nexperia PUMH10,115 is a dual NPN Resistor-Equipped Transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mount package. It integrates two independent NPN transistors with built-in bias resistors: R1 at 2.2 kΩ and R2 at 47 kΩ. The device supports a maximum collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation reaches 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. Junction temperatures are rated up to 150 °C.
Verify the specific ordering suffix against official Nexperia documentation to confirm packaging details such as reel size or tape dimensions. Confirm that the requested variant matches the required marking code and manufacturing site specifications before finalizing procurement orders.
Select this component when a dual NPN configuration with integrated biasing is required for space-constrained designs. Ensure the 2.2 kΩ input resistor value aligns with the target logic levels and drive currents. Verify thermal requirements against the 300 mW total dissipation limit under expected operating conditions.
This part belongs to the PUMH series of NPN/NPN resistor-equipped double transistors. Complementary configurations include the PUMD10 for NPN/PNP pairs and the PUMB10 for PNP/PNP pairs. All variants share similar electrical characteristics and package dimensions while differing in transistor polarity and internal resistor values.
Direct substitutes within the same family include PUMH11 and PUMH9, which offer different bias resistor ratios. Cross-family replacements like PEMH24 provide identical pinouts but utilize different resistor values (100 kΩ). Verify compatibility with existing PCB footprints and thermal management strategies.