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The Nexperia PUMH10Z is a dual NPN Resistor-Equipped Transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mount package. It integrates two NPN transistors with built-in bias resistors, specifically R1 = 2.2 kΩ and R2 = 47 kΩ per transistor. The device supports a maximum collector-emitter voltage of 50 V and an output current capability of 100 mA per transistor. Total power dissipation is rated at 300 mW at 25 °C ambient temperature. Key electrical characteristics include a DC current gain (hFE) minimum of 100 at 10 mA and 5 V, and a collector-emitter saturation voltage of 100 mV maximum at 5 mA collector current.
Verify the specific ordering suffix 'Z' against the official Nexperia datasheet or distributor catalog to confirm packaging configuration, as standard listings may default to tape-and-reel formats without explicit suffix notation. Confirm RoHS compliance status and moisture sensitivity level prior to procurement to ensure compatibility with assembly processes.
Select this component when a dual NPN configuration with integrated biasing is required to minimize board space and assembly steps. Ensure the 50 V breakdown voltage and 100 mA current limits align with the target application's electrical requirements. Consider the thermal resistance characteristics if operating near the maximum power dissipation limit.
The PUMH10Z belongs to the Nexperia PUMH10 family of resistor-equipped double transistors. It serves as the NPN/NPN variant within this series, complemented by the PUMD10 (NPN/PNP) and PUMB10 (PNP/PNP) types. This family is designed to replace multiple discrete components in digital switching and signal conditioning roles.
Direct functional equivalents include the PUMH10 from other manufacturers with identical pinout and electrical specifications. Verify that any substitute maintains the same R1 (2.2 kΩ) and R2 (47 kΩ) values and fits within the SOT363-3 package dimensions.