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The Nexperia PUMH11,115 is a dual NPN resistor-equipped transistor (RET) housed in a SOT363-3 (TSSOP6) surface-mount package. It integrates two NPN transistors with built-in bias resistors, where R1 is nominally 10 kΩ and the R2/R1 ratio is unity. The device supports a maximum collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is rated at 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. The component operates within a junction temperature range up to 150 °C.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact reel quantity and tape-and-reel specifications. Confirm that the requested part number matches the SOT363-3 package variant, as revision history indicates potential package designation changes between SOT363 and SOT363-3. Ensure compliance with RoHS3 standards if required for the target assembly process.
Select this component when space constraints require a dual NPN configuration with integrated biasing in a 6-lead surface-mount footprint. The 10 kΩ input resistance is suitable for standard logic interface levels. Verify that the 50 V collector-emitter voltage rating meets the circuit requirements. Consider the total power dissipation limits when designing thermal management for high-density PCB layouts.
The PUMH11 belongs to Nexperia's family of NPN/NPN Resistor-Equipped Transistors. It serves as the NPN/NPN complement to the PUMD3 (NPN/PNP) and PUMB11 (PNP/PNP) variants. All devices share similar electrical characteristics and are designed for cost-effective digital switching applications requiring minimal external components.
Direct functional substitutes include other NPN/NPN RETs in SOT363 packages from Nexperia, such as the PUMH9 or PUMH7 series, provided the internal resistor values match the design requirements. Cross-manufacturer equivalents must be verified for pin compatibility and electrical parameters.