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The Nexperia PUMH11F is a dual NPN resistor-equipped transistor (RET) housed in a SOT363-3 (TSSOP6) surface-mounted package. It integrates two NPN transistors with built-in bias resistors, where R1 is nominally 10 kΩ and the R2/R1 ratio is 1. The device supports a maximum collector-emitter voltage (VCEO) of 50 V and an output current (IO) of 100 mA per transistor. Total power dissipation is rated at 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. The junction temperature range extends from -65 °C to +150 °C.
Verify the specific suffix 'F' against the manufacturer's official ordering information to confirm packaging details such as reel or cut tape specifications. Ensure the procurement documentation references the latest product data sheet version to account for any recent package changes from SOT363 to SOT363-3.
Select this component when space constraints require a dual NPN configuration with integrated base resistors. The 10 kΩ input resistance is suitable for standard logic interface levels. Verify that the required collector current does not exceed 100 mA and that the thermal environment allows for the specified 300 mW total power dissipation rating.
The PUMH11 belongs to Nexperia's family of Resistor-Equipped Transistors (RETs). It serves as the NPN/NPN complement to the PUMD3 (NPN/PNP) and PUMB11 (PNP/PNP) variants. These devices are designed to replace multiple discrete components in compact surface-mount designs.
Direct functional equivalents include the PUMH9 and PUMH7 series, though these differ in internal resistor values. Cross-reference the pinout and electrical characteristics carefully before substitution.