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The Nexperia PUMH16,115 is a dual NPN resistor-equipped transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mount package. It integrates two NPN transistors with built-in bias resistors: R1 is nominally 22 kΩ and R2 is nominally 47 kΩ. The device supports a collector-emitter voltage of 50 V and a maximum output current of 100 mA per transistor. Total power dissipation is rated at 300 mW. It meets AEC-Q101 automotive qualification standards.
Verify the specific ordering suffix matches the required packaging format, such as tape and reel or cut tape, before placing orders. Confirm that the manufacturing site code aligns with project requirements. Ensure the design accounts for the specified thermal resistance values when mounted on FR4 PCBs to maintain safe operating junction temperatures under load conditions.
Select this component when a compact dual NPN solution with integrated base biasing is required. The fixed 22 kΩ input resistor simplifies drive circuit calculations. Verify that the 50 V collector-emitter breakdown voltage and 100 mA current limits exceed the maximum expected operational stresses in the target application environment.
The PUMH16 belongs to Nexperia's family of NPN/NPN Resistor-Equipped Transistors. Its PNP/PNP complement is the PUMB16, while the NPN/PNP variant is the PUMD16. All members share the same SOT363-3 footprint, facilitating design flexibility within mixed-signal circuits requiring complementary logic levels.
Direct functional substitutes include the PUMB16 for PNP/PNP configurations and the PUMD16 for NPN/PNP arrangements. Other RETs in the same SOT363-3 package may serve as alternatives if resistor values and electrical ratings are compatible.
The internal bias resistor R1 is nominally 22 kΩ, and the ratio R2/R1 is nominally 2.1, resulting in an R2 value of approximately 47 kΩ.
Yes, the device is qualified in accordance with the AEC-Q101 standard for discrete semiconductors, making it suitable for automotive applications.
The TSSOP6 (SOT363-3) package has six leads, providing connections for two independent transistors including bases, collectors, and emitters.