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The PUMH17F is a dual NPN resistor-equipped transistor (RET) housed in a SOT363 (SC-88) surface-mount package. It integrates two NPN transistors with built-in bias resistors, specifically R1 at 47 kΩ and R2 at 22 kΩ. Key electrical parameters include a collector-emitter voltage of 50 V, a DC output current of 100 mA, and a total power dissipation of 300 mW at 25 °C ambient temperature. The device features a minimum DC current gain of 60 at 5 mA and 5 V, with a maximum collector-emitter saturation voltage of 150 mV at 10 mA collector current.
Verify the specific suffix 'F' against the official Nexperia datasheet to confirm it denotes the standard SOT363 packaging variant without additional functional changes. Confirm RoHS compliance status and ensure the ordering code matches the required packing method for automated assembly processes.
Select this component when space constraints require integrating biasing resistors directly with the transistor array. Ensure the application operates within the 50 V collector-emitter voltage limit and 100 mA current rating. Verify that the thermal resistance characteristics are sufficient for the expected ambient temperature conditions.
The PUMH17F belongs to the PEMH17/PUMH17 family of NPN/NPN resistor-equipped transistors. While the PEMH17 utilizes the SOT666 package, the PUMH17 variant specifically uses the SOT363 (SC-88) plastic surface-mounted package. This family is designed to replace discrete transistor and resistor combinations in digital logic circuits.
Direct replacements include PEMH17 (SOT666 package) or other NPN/NPN RETs with similar 47 kΩ/22 kΩ bias ratios and 50 V ratings from compatible manufacturers, provided pinout compatibility is verified.