PUMH18,115

Overview

The Nexperia PUMH18,115 is a dual NPN Resistor-Equipped Transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mounted package. It integrates two NPN transistors with built-in bias resistors, specifically R1 at 4.7 kΩ and an R2/R1 ratio of 2.1. The device supports a collector-emitter voltage (VCEO) of 50 V and a continuous output current (IO) of 100 mA per transistor. Total power dissipation reaches 300 mW at 25 °C ambient temperature, with a maximum junction temperature of 150 °C. The component is AEC-Q101 qualified for automotive applications.

Feature Summary

• Integrates dual NPN transistors with fixed internal bias resistors to reduce external component count
• AEC-Q101 qualified for automotive reliability standards
• Compact SOT363-3 package minimizes PCB footprint and pick-and-place costs

Applications

• Low current peripheral driver circuits
• Control of IC inputs
• Replacement of general-purpose transistors in digital logic applications

Procurement Notes

Verify the specific ordering suffix

Selection Notes

Select this RET when circuit design requires dual NPN switching with integrated base biasing. The fixed 4.7 kΩ input resistor simplifies drive requirements. Ensure the 50 V voltage rating and 100 mA current capacity align with load specifications. Consider the SOT363-3 thermal characteristics for high-density layouts.

Part Context

The PUMH18 belongs to Nexperia's family of NPN/NPN resistor-equipped double transistors. Complementary variants include the PUMD18 (NPN/PNP) and PUMB18 (PNP/PNP). These devices share similar packaging and electrical architectures but differ in transistor polarity configurations to support various logic interface needs.

Replacement Considerations

Direct functional substitutes within the same Nexperia portfolio include PUMD18 and PUMB18, depending on required polarity. Cross-manufacturer replacements require matching VCEO, IO, and package dimensions while verifying internal resistor values.