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The Nexperia PUMH20,115 is a dual NPN Resistor-Equipped Transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mount package. It integrates two independent NPN transistors with built-in bias resistors, each having a typical resistance of 2.2 kΩ. The device supports a maximum collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is rated at 300 mW at 25 °C ambient temperature. The component operates within an ambient temperature range of -65 °C to +150 °C and features a junction temperature limit of 150 °C.
Verify the specific ordering suffix to confirm package type and reel specifications. Confirm that the product status matches the intended production volume requirements. Check for any recent revision history updates regarding qualification status or testing standards before finalizing procurement orders.
Select this component when space constraints require a dual-transistor solution with integrated base resistors. Ensure the required input resistance aligns with the 2.2 kΩ nominal value. Verify that the 50 V collector-emitter voltage rating meets the circuit's maximum operating conditions.
This part belongs to Nexperia's family of resistor-equipped transistors designed for digital logic interfacing. It serves as a compact alternative to discrete transistor and resistor combinations. The PUMH20 specifically provides a dual NPN configuration, offering complementary options such as the PUMD20 for NPN/PNP configurations.
Direct functional replacements include other dual NPN RETs with similar voltage and current ratings. Verify pinout compatibility with the SOT363-3 package. Consider the PUMH24 if a higher bias resistance value is required.