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The PUMH4,115 is a dual NPN resistor-equipped transistor (RET) housed in a TSSOP6 (SOT363) surface-mount package. It integrates two NPN transistors with built-in bias resistors, where R1 is nominally 10 kΩ and R2 is open. The device supports a collector-emitter voltage of 50 V and a continuous collector current of 100 mA per transistor. Total power dissipation reaches 300 mW for the device at 25 °C ambient temperature. It features a DC current gain (hFE) of at least 200 at 1 mA and 5 V. The component is qualified to AEC-Q101 standards for automotive applications.
Verify the specific ordering suffix against the manufacturer's latest documentation to confirm packaging details and manufacturing site codes. Ensure compatibility with standard reflow soldering profiles for the SOT363 package. Confirm that the application environment remains within the specified thermal resistance and power derating limits defined in the datasheet.
Select this component when space constraints require a dual NPN configuration with integrated base resistors. The 10 kΩ input resistor value suits standard logic interface levels. Consider the 50 V breakdown voltage and 100 mA current rating for low-power switching tasks. Verify that the open R2 configuration meets the specific bias requirements of the target circuit design.
The PUMH4 belongs to Nexperia's Resistor-Equipped Transistor (RET) family designed for compact digital switching. It serves as the NPN/NPN variant within the PUMH series. Complementary devices include the PUMD4 for NPN/PNP configurations and the PUMB4 for PNP/PNP arrangements. All share the same SOT363 footprint for board layout consistency.
Publicly confirmed substitute part numbers are not available in the provided source material.