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The RC19020AGN6#KD0 is a PCIe Gen7 compliant clock buffer featuring one differential input and twenty LP-HCSL outputs. It operates within a frequency range of 1 MHz to 400 MHz on a single 3.3 V supply, consuming approximately 716 mW. The device supports LVDS and HCSL inputs and provides selectable output slew rates via SMBus. Key features include power down tolerance, flexible startup sequencing, automatic clock parking, and open-drain loss-of-signal indication. It is housed in an 80-GQFN package measuring 6 mm x 6 mm.
Verify the specific ordering suffix #KD0 against official Renesas documentation to confirm packaging details such as reel quantity and carrier type. Ensure the 80-GQFN package dimensions match the design footprint requirements. Confirm that the -40°C to +105°C operating temperature range aligns with the target application environment.
Select this component for designs requiring high fan-out from a single reference clock to multiple PCIe endpoints. The backward compatibility with earlier PCIe generations allows for versatile use across different system generations. Verify that the input signal type matches the available LVDS or HCSL sources and that the 3.3 V supply voltage is stable within the specified 2.97 V to 3.63 V range.
This part belongs to the RC190xxA family of PCIe clock buffers. It is pin-compatible with the DB2000Q/DB2000QL plus, adding Loss-Of-Signal (LOS) indication and an SBI_OUT pin for daisy-chaining multiple clock chips. This compatibility simplifies migration from previous generation designs while offering enhanced monitoring capabilities.
The RC19020 is pin-compatible with the DB2000Q and DB2000QL plus. Designers migrating from these devices should verify that the additional LOS and SBI_OUT pins are correctly handled in the new layout.