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SC28L92A1BS,528 is listed in the UARTs (Universal Asynchronous Receiver Transmitter) range at ChipApex. The manufacturer field lists NXP USA Inc.. Its product description is IC UART DUAL W/FIFO 48HVQFN. Review the specifications below when checking this part for your BOM.
The SC28L92A1BS,528 is a Dual Universal Asynchronous Receiver/Transmitter (DUART) from NXP Semiconductors. It operates on a single 3.3 V or 5 V supply and supports data transfer rates up to 1 Mbit/s. The device features two independent full-duplex channels, each equipped with 16-byte FIFOs for both reception and transmission. It provides pin-programmable compatibility with Intel (80xxx) and Motorola (68xxx) bus interfaces. The component includes an on-chip crystal oscillator, programmable baud rate generators, and a versatile interrupt system.
Verify the specific ordering suffix matches the HVQFN48 package variant. Confirm that the required temperature range aligns with the industrial specification of -40 °C to +85 °C. Ensure the design accommodates the exposed thermal pad requirements for proper grounding and heat dissipation in the selected package configuration.
Select this component when replacing legacy SCC2692 or SC26C92 devices while requiring deeper FIFO buffers. Choose the 80xxx mode if interfacing with Intel-compatible processors, or the 68xxx mode for Motorola-compatible buses. Consider the HVQFN48 package for space-constrained designs requiring enhanced thermal performance.
This part belongs to the SC28L92 family within the IMPACT product line. It serves as a direct pin and function replacement for older UART models but offers extended capabilities such as faster speeds and additional control registers. The device is designed to power up in a configuration compatible with the SC26C92 to facilitate easier migration.
SC28L92A1B
The bus interface is determined by the logic level on the I/M pin. Connecting I/M to HIGH configures the device for the 80xxx (Intel) interface, while connecting it to LOW selects the 68xxx (Motorola) interface.
Yes, the FIFO capacity can be configured for either 8 bytes or 16 bytes per channel. This setting is controlled by bit 3 of the Mode Register 0 (MR0A).
The device supports an internal crystal oscillator connected across X1/CLK and X2 pins, or an external clock signal applied directly to the X1/CLK input.
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