SI5010-B-GMR

Overview

The Si5010-B-GMR is a fully integrated clock and data recovery (CDR) IC designed for OC-12/3 and STM-4/1 SONET/SDH applications. It operates from a single 2.5 V supply with typical power dissipation of 293 mW at OC-12 rates. The device utilizes DSPLL technology to eliminate external loop filter components, ensuring low jitter generation of 1.6 mUI rms. It features differential CML inputs and outputs, LVTTL control interfaces, and supports multi-rate operation via the RATESEL pin. Packaged in a 20-lead 4x4 mm QFN, it functions within an industrial temperature range of –40 to 85 °C.

Feature Summary

• DSPLL technology eliminates external loop filter components for optimal jitter performance
• Supports OC-12/3 (155.52 Mbps) and STM-4/1 (622.08 Mbps) data rates
• Low power consumption: 293 mW typical at OC-12, 310 mW at OC-3
• Jitter generation of 1.6 mUI rms (typical) exceeding SONET/SDH specifications

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• Board level serial links
• SONET/SDH test equipment
• Optical transceiver modules
• SONET/SDH regenerators

Procurement Notes

Verify the ordering suffix 'GMR' indicates tape and reel packaging with 2500 units per reel. Confirm the 'B' revision code matches the required die version. Ensure the component is sourced from authorized distributors to guarantee RoHS compliance and lead finish integrity. Check for end-of-life notifications as older revisions may be discontinued.

Selection Notes

Select this device for high-speed serial links requiring strict SONET/SDH jitter compliance without external analog filters. Ensure the system provides a stable 2.5 V supply within ±5% tolerance. Verify that the reference clock frequency (19.44 MHz, 77.76 MHz, or 155.52 MHz) matches the application requirements. Use the RATESEL pin to configure the specific data rate mode.

Part Context

The Si5010 belongs to the Silicon Laboratories CDR family, specifically optimized for OC-12/3 and STM-4/1 speeds. It replaces traditional PLL designs by integrating the loop filter digitally via DSPLL. The 'B' suffix denotes a specific product revision, while 'GM' indicates the 20-lead QFN package. This part is distinct from higher-speed variants like the Si5020.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Designers should verify compatibility with existing board layouts if substituting with other CDR devices, particularly regarding the 4x4 mm QFN footprint and pinout differences.

FAQ

How is the internal bias current set?

The internal bias currents are set by connecting a 10 kΩ (1%) resistor between the REXT pin and GND.

What is the function of the PWRDN/CAL pin?

Driving PWRDN/CAL high disables the device and reduces power consumption. Driving it low initiates a self-calibration sequence if a valid reference clock is present.

How does the device handle loss of lock?

The LOL pin asserts high when the recovered clock frequency deviates from the reference clock by more than 450–750 ppm, indicating the PLL is out of lock.