SI5017-BM

Overview

The Si5017 is a fully integrated clock and data recovery (CDR) IC with an embedded limiting amplifier, designed for OC-48/STM-16 SONET/SDH applications. It supports data rates up to 2.7 Gbps for FEC implementations. The device utilizes DSPLL technology to eliminate external loop filter components, reducing board-level noise susceptibility. Operating from a single 3.3 V supply over the industrial temperature range of –40 °C to 85 °C, it features low jitter generation of 3.0 mUIrms typical. Key electrical parameters include a differential input sensitivity of 10 mVpp and output voltage swings of 800 mVpp.

Feature Summary

• Integrates high-speed limiting amplifier and CDR for OC-48/STM-16 and 2.7 Gbps FEC
• DSPLL technology eliminates external loop filter components for superior jitter performance
• Low power consumption of 528 mW typical at 3.3 V supply
• Supports both reference clock and reference-less operation modes

Applications

• SONET/SDH routers and add/drop multiplexers
• Digital cross-connect systems
• Board-level serial links
• Optical transceiver modules
• SONET/SDH test equipment and regenerators

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and tape/reel specifications. Confirm availability status as distribution channels may vary. Ensure the design incorporates the required 10 kΩ bias resistor on the REXT pin and proper grounding of the exposed pad for thermal and electrical performance.

Selection Notes

Select this component for designs requiring OC-48 or STM-16 signal regeneration with minimal external passive components. Verify that the application can accommodate the 28-pin micro leaded package (MLP) footprint. Ensure the system provides a stable 3.3 V supply within the specified tolerance and consider the need for an external reference clock to minimize acquisition time if required by the network architecture.

Part Context

The Si5017 belongs to a family of high-speed serial communication ICs developed using Silicon Laboratories' proprietary DSPLL technology. This approach replaces traditional analog loop filters with digital signal processing algorithms to adjust the VCO frequency. The device is specifically engineered to meet Bellcore GR-253-CORE and ITU-T G.958 jitter compliance standards for SONET/SDH equipment.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided source material. Evaluate alternative CDRs based on compatible interface voltages, package dimensions, and jitter tolerance masks.