SI5017-D-GM

Overview

The SI5017-D-GM is a fully integrated clock and data recovery (CDR) IC with an embedded limiting amplifier, designed for OC-48/STM-16 SONET/SDH applications. It supports data rates up to 2.7 Gbps when utilizing Forward Error Correction (FEC). The device utilizes Silicon Laboratories DSPLL technology to eliminate external loop filter components, thereby reducing jitter generation to a typical value of 3.0 mUIrms. Operating from a single 3.3 V supply within the industrial temperature range of –40 °C to 85 °C, it features differential CML inputs and outputs. Key functional blocks include lock detection, loss-of-signal monitoring, and bit-error-rate alarms.

Feature Summary

• Integrated Limiting Amplifier and CDR supporting OC-48/STM-16 and 2.7 Gbps FEC
• DSPLL Technology eliminates external loop filters for superior jitter performance
• Low power consumption with typical dissipation of 528 mW at OC-48 rates
• Small 5 x 5 mm footprint in a 28-pin micro leaded package

Applications

• SONET/SDH routers and add/drop multiplexers
• Digital cross-connect systems
• Board-level serial links
• Optical transceiver modules
• SONET/SDH regenerators and test equipment

Procurement Notes

The SI5017-D-GM is identified as a discontinued product by the manufacturer. Verification of availability requires checking authorized distributors for remaining stock or surplus inventory. Designers should confirm end-of-life status and plan for component obsolescence management prior to procurement.

Selection Notes

Select this component for high-speed serial communication systems requiring low jitter recovery without external analog loop filters. Ensure the application operates within the 3.135 V to 3.465 V supply range and –40 °C to 85 °C temperature limits. Verify that the input signal meets the minimum differential swing requirements specified in the electrical characteristics table.

Part Context

This part belongs to the Si5017 series of high-speed CDRs developed using DSPLL technology. It is distinct from programmable oscillators (Si501/2/3/4) or other power management ICs sharing similar numerical prefixes. The 'D' suffix typically denotes specific packaging or temperature grade variations within the Skyworks/Silicon Labs portfolio.

Replacement Considerations

As a discontinued component, direct replacements are not officially listed in the provided documentation. Engineers must evaluate alternative CDRs with compatible pinouts, DSPLL-like architecture, and support for OC-48/STM-16 rates. Cross-referencing with newer generations of SONET/SDH retimers is recommended.

FAQ

How is the Loss-of-Signal (LOS) threshold configured?

The LOS threshold is set by applying a voltage to the LOS_LVL pin. A voltage between 1.50 V and 2.50 V maps to a threshold range of 0 to 40 mVpp. Applying less than 1 V disables the LOS function.

What is the purpose of the LTR input?

The Lock-to-Reference (LTR) input forces the PLL to lock to an external reference clock when asserted. This maintains a stable output clock during alarm conditions such as Loss-of-Signal.

Can the Si5017 operate without an external reference clock?

Yes, the device can perform clock and data recovery without an external reference. This is configured by tying REFCLK+ to VDD and REFCLK– to GND, though acquisition time may be longer compared to reference-based operation.