SI5018-B-GM

Overview

The Si5018-B-GM is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/STM-16 data rates, supporting up to 2.7 Gbps with forward error correction (FEC). The device operates from a single 2.5 V supply over the industrial temperature range of –40 to 85 °C. Key electrical specifications include a typical power dissipation of 270 mW at OC-48, an output clock rate of 2.4–2.7 GHz, and a typical RMS jitter generation of 3.0 mUI.

Feature Summary

• DSPLL™ technology eliminates external loop filter components by using digital signal processing to adjust the VCO frequency.
• Supports OC-48/STM-16 standards and FEC applications up to 2.7 Gbps.
• Exceeds SONET/SDH jitter specifications with typical RMS jitter generation of 3.0 mUI.
• Features 3.3 V tolerant control inputs and a loss-of-lock indicator.

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• SONET/SDH test equipment
• Optical transceiver modules

Procurement Notes

Verify the ordering suffix 'GM' corresponds to the 20-lead QFN package with lead-free compliance. Confirm the revision letter 'B' matches the required silicon version. Ensure the application circuit includes the recommended 10 kΩ bias resistor on the REXT pin and proper grounding of the bottom thermal pad.

Selection Notes

Select this component for designs requiring low jitter performance in OC-48/STM-16 environments. The DSPLL architecture simplifies PCB layout by removing analog loop filter components. Ensure the reference clock frequency falls within the 19.44 MHz to 168.75 MHz range to support the desired data rate and FEC configuration.

Part Context

The Si5018 is part of the SiPHY family of CDR devices from Silicon Laboratories. The '-B-' designation indicates a specific silicon revision, while '-GM' denotes the 20-lead Quad Flat No-Lead (QFN) package. This device is engineered to replace traditional PLL-based CDRs that require complex external filtering.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

FAQ

How is the internal self-calibration initiated?

Self-calibration is initiated by forcing a high-to-low transition on the PWRDN/CAL pin while a valid reference clock is supplied. The pin must be held high for at least 1 µs before transitioning low.

What is the function of the REXT pin?

The REXT pin is used to connect an external 10 kΩ (1%) resistor to ground. This resistor sets the internal bias currents, which reduces power consumption compared to implementations using internal resistors.

How does the Loss-of-Lock (LOL) indicator work?

The LOL pin is driven high when the recovered clock frequency deviates from the reference clock by more than the specified threshold (e.g., 450–750 ppm). It indicates that the PLL has lost frequency lock with the incoming data stream.