SI5018-BM

Overview

The Si5018-BM is a fully integrated low-power Clock and Data Recovery (CDR) IC designed for high-speed serial communication systems operating at OC-48/STM-16 rates. It utilizes DSPLL™ technology to eliminate external loop filter components, ensuring optimal jitter performance. The device supports data streams up to 2.7 Gbps with Forward Error Correction (FEC). It operates from a single 2.5 V supply over the industrial temperature range of –40 to 85 °C. Key electrical parameters include a typical power dissipation of 270 mW, an output clock rate of 2.4–2.7 GHz, and RMS jitter generation of 3.0 mUI.

Feature Summary

• DSPLL™ Technology: Eliminates external loop filter components using digital signal processing to reduce noise susceptibility.
• Low Power Consumption: Typical power dissipation of 270 mW at OC-48 rates.
• High-Speed Operation: Supports OC-48/STM-16 data rates up to 2.7 Gbps with FEC support.
• Compliance: Exceeds SONET/SDH jitter specifications per Bellcore GR-253-CORE and ITU-T G.958.

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• SONET/SDH test equipment
• Optical transceiver modules

Procurement Notes

Verify the package type matches the 20-pin Micro Leadframe Package (MLP) with a 4x4 mm footprint. Confirm the temperature grade corresponds to the industrial range (-40 to 85 °C). Ensure the ordering suffix aligns with the specific die revision and designator required for the application.

Selection Notes

Select this component for applications requiring low jitter CDR solutions in SONET/SDH environments. The DSPLL™ feature simplifies PCB layout by removing external analog loop filter components. Ensure the system reference clock falls within the specified range of 19.44 MHz to 168.75 MHz for proper PLL centering.

Part Context

The Si5018-BM is part of the SiPHY™ family of OC-48/STM-16 CDR ICs with FEC. It is manufactured by Silicon Laboratories Inc. The 'BM' suffix denotes the 20-pin MLP package variant suitable for surface mount assembly.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Evaluate compatibility based on pinout, electrical specifications, and package dimensions if considering alternative CDR devices.

FAQ

How is the internal self-calibration initiated?

Self-calibration is initiated by forcing a high-to-low transition on the PWRDN/CAL pin while a valid reference clock is supplied. The pin must be held high for at least 1 µs before transitioning low.

What is the function of the REXT pin?

The REXT pin is used to connect an external 10 kΩ (1%) resistor to GND. This resistor sets the internal bias currents, which significantly reduces power consumption compared to implementations using internal resistors.

How does the Loss-of-Lock (LOL) indicator work?

The LOL pin is driven high when the recovered clock frequency deviates from the reference clock by more than the specified threshold (e.g., 450-750 ppm). It indicates that the PLL has lost frequency lock with the incoming data stream.