SI5020-BM

Overview

The Si5020-BM is a fully integrated, low-power Clock and Data Recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information from serial inputs at OC-48/12/3, STM-16/4/1, Gigabit Ethernet, or 2.7 Gbps FEC rates. Operating from a single 2.5 V supply over the industrial temperature range (-40 to 85 °C), it features DSPLL technology to eliminate external loop filter components. Typical power dissipation is 270 mW at OC-48. The device provides differential CML outputs for recovered data and clock, with 3.3 V tolerant control inputs.

Feature Summary

• DSPLL™ Technology: Eliminates external PLL loop filter components using digital signal processing to reduce noise susceptibility and ensure optimal jitter performance.
• Multi-Rate Support: Handles OC-48/STM-16 (up to 2.7 Gbps with FEC), OC-12, OC-3, and Gigabit Ethernet via RATESEL pin configuration.
• Low Jitter Generation: Typically generates 2.9 mUI rms jitter when presented with jitter-free input data.
• Integrated Self-Calibration: Features internal circuitry for PLL self-calibration upon power-up to set loop gain parameters.

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• Gigabit Ethernet interfaces
• Optical transceiver modules

Procurement Notes

Verify the package marking matches 'Si5020-BM' to confirm the 20-pin MLP variant. Confirm the operating temperature range requirement aligns with the specified -40 to 85 °C industrial grade. Ensure the system design accommodates the single 2.5 V supply voltage and the specific PCB layout requirements for the thermal pad grounding.

Selection Notes

Select this component for applications requiring SONET/SDH or Gigabit Ethernet clock recovery without external analog loop filters. The multi-rate capability allows flexibility across OC-3, OC-12, and OC-48 speeds. Ensure the reference clock frequency falls within the 19.44 MHz to 168.75 MHz range to support the internal VCO centering logic.

Part Context

The Si5020-BM is part of the Silicon Laboratories SiPHY family of CDR devices. The '-BM' suffix specifically denotes the 20-pin Micro Leadframe Package (MLP) with dimensions of 4 mm x 4 mm. This package requires specific PCB layout guidelines for the central ground pad to ensure proper thermal dissipation and electrical grounding.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult official Silicon Laboratories resources for current replacement recommendations.

FAQ

How is the PLL self-calibration initiated?

Self-calibration is initiated by forcing a high-to-low transition on the PWRDN/CAL pin while a valid reference clock is supplied. The pin must be held high for at least 1 µs before transitioning low.

What is the function of the REXT pin?

The REXT pin is used to connect an external 10 kΩ (1%) resistor to GND. This resistor sets the internal bias currents for the device, which helps reduce power consumption compared to implementations using internal resistors.

How does the device handle Loss-of-Lock (LOL)?

The LOL output is driven high when the recovered clock frequency deviates from the reference clock by more than the specified threshold (e.g., 450-750 ppm). In this state, the PLL periodically attempts to reacquire lock.