SI53112-A00AGMR

Overview

The Si53112-A00AGMR is a low-power, 12-output differential clock buffer designed to meet Intel DB1200ZL specifications. It operates at 100 MHz or 133 MHz with a VDD supply of 3.3V ± 5% and VDD_IO ranging from 1.05V to 3.3V. The device features twelve 0.7V push-pull HCSL-compatible outputs, achieving 50 ps output-to-output skew and 50 ps cyc-cyc jitter in PLL mode. It supports SMBus configuration for nine selectable addresses and includes individual hardware output enable pins for each channel.

Feature Summary

• Twelve 0.7V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs
• Individual OE HW pins for each output clock
• 100 MHz / 133 MHz PLL operation, supports PCIe and QPI
• 9 selectable SMBUS addresses

Applications

• Server
• Storage
• Datacenter
• Enterprise Switches and Routers

Procurement Notes

Verify the A00A ordering suffix against the manufacturer's current documentation to confirm specific factory configurations or revisions. Ensure the component matches the 64-pin QFN package outline and land pattern requirements specified in the datasheet before integration into the design.

Selection Notes

Select this component for designs requiring compliance with Intel DB1200ZL specifications. Confirm that the system utilizes a 1:1 frequency ratio between input and output clocks. Verify that the host controller supports SMBus communication for address selection and bandwidth configuration via the HBW_BYPASS_LBW pin.

Part Context

The Si53112 is part of Skyworks Solutions' portfolio of precision clock buffers. It is optimized for distributing reference clocks for Intel Quick-Path Interconnect (QPI), PCIe Gen 1/2/3/4, SAS, SATA, and Intel Scalable Memory Interconnect (SMI) applications.

Replacement Considerations

Consult Skyworks Solutions directly for higher output count devices or variations of this component. No public substitute part numbers are documented in the provided datasheet.