SI53115-A01AGMR

Overview

The SI53115-A01AGMR is a 15-output, low-power HCSL differential clock buffer designed for high-speed interface applications. It meets Intel DB1200ZL specifications and supports PCIe Gen 1/2/3/4, SAS, SATA, Intel QPI, and SMI. The device operates at 100 MHz or 133 MHz with a VDD/VDD_A supply of 3.135 V to 3.465 V and VDD_IO from 1.05 V to 3.465 V. Key electrical parameters include 50 ps output-to-output skew, 50 ps cyc-cyc jitter in PLL mode, and 100 ps input-to-output delay. It features SMBus programmability for output enable control and address selection within a 64-pin QFN package.

Feature Summary

• 15-output low-power push-pull HCSL buffers compliant with PCIe Gen3 SRNS
• Integrated PLL optimized for 100 MHz and 133 MHz operation
• SMBus configurable outputs and selectable addresses (9 options)
• Supports PLL, bypass, and spread spectrum modes

Applications

• Intel QuickPath Interconnect (QPI) reference distribution
• PCIe Gen 1/2/3/4 server and storage systems
• Data center enterprise switches and routers
• Intel Scalable Memory Interconnect (SMI)

Procurement Notes

Verify the datasheet revision (Rev 1.2) and specific ordering suffixes against Skyworks documentation. Confirm that the A01A suffix corresponds to the intended frequency configuration and pinout requirements for the target PCB layout. Ensure compatibility with standard SMBus voltage levels if interfacing with controllers operating at different logic voltages.

Selection Notes

Select this component when distributing reference clocks for high-speed serial interfaces requiring low jitter and zero-delay buffering. The choice between PLL and bypass modes depends on the input clock quality; use PLL mode for jitter reduction and bypass mode for minimal additive jitter. Ensure the design accommodates the separate VDD and VDD_IO power rails to meet the specified AC timing characteristics.

Part Context

This part belongs to the Si53115 family of PCI Express Gen3 clock buffers. It serves as a fan-out buffer solution for platforms requiring multiple synchronized clock domains. The device integrates a VCO and SMBus interface to replace discrete buffer solutions, reducing board space and simplifying power management in complex server architectures.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided source material.