SI5315A-C-GMR

Overview

The Si5315A-C-GMR is a jitter-attenuating clock multiplier utilizing Skyworks DSPLL technology. It accepts dual differential clock inputs from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied outputs within the same range. The device supports SyncE EEC options 1 and 2, offering ultra-low jitter generation of 0.23 ps RMS (1.875–20 MHz) for the Si5315A speed grade. It features programmable output formats including LVPECL, LVDS, CML, and CMOS, with selectable loop bandwidths between 60 Hz and 8.4 kHz. Powered by a single 1.8 V, 2.5 V, or 3.3 V supply, it operates in a 36-pin QFN package across a –40 to +85 °C temperature range.

Feature Summary

• Dual-input, dual-output architecture supporting frequencies up to 644.53 MHz
• Ultra-low jitter generation: 0.23 ps RMS (1.875–20 MHz) for Si5315A
• Hitless switching and holdover capabilities compliant with ITU-T G.8262
• Programmable output signal formats: LVPECL, LVDS, CML, or CMOS

Applications

• Synchronous Ethernet line cards
• SONET OC-3/12/48 line cards
• PON OLT/ONU systems
• Carrier Ethernet switches and routers
• T1/E1/DS3/E3 line cards

Procurement Notes

Verify the specific speed grade suffix (e.g., A or B) against design requirements, as performance metrics like jitter generation vary between grades. Confirm the 'GMR' suffix indicates tape-and-reel packaging suitable for automated surface-mount assembly. Ensure the selected voltage supply aligns with the device's operating range of 1.8 V, 2.5 V, or 3.3 V.

Selection Notes

Select the Si5315A variant for applications requiring lower jitter generation (0.23 ps RMS). Choose the Si5315B variant if higher maximum output frequencies are not required but cost optimization is prioritized. Verify that the external crystal or reference clock input matches the supported frequency range of 8 kHz to 644.53 MHz. Ensure the load capacitance and drive strength requirements of the destination PHY match the programmable output format settings.

Part Context

The Si5315 belongs to Skyworks Solutions' family of synchronous Ethernet and telecom jitter attenuating clock multipliers. It replaces discrete PLL solutions by integrating the VCXO and loop filter components on-chip. The device is designed to synchronize line card clocks to centralized backplane references while filtering jitter to meet strict telecom standards.

Replacement Considerations

Direct pin-compatible replacements within the same series include other Si5315 variants with different speed grades or packaging options. Cross-family replacements may require schematic redesign due to differences in pinout, power supply requirements, or control interfaces.