SI5315B-C-GM

Overview

The Skyworks SI5315B-C-GM is a jitter-attenuating clock multiplier utilizing third-generation DSPLL technology. It accepts dual differential clock inputs from 8 kHz to 644 MHz and generates two equal frequency-multiplied outputs within the same range. The device supports SyncE EEC options 1 and 2, providing ultra-low jitter generation of 0.23 ps RMS (1.875–20 MHz). It features programmable output formats including LVPECL, LVDS, CML, and CMOS, with selectable loop bandwidths between 60 Hz and 8.4 kHz for optimized jitter performance.

Feature Summary

• Dual input/dual output architecture supporting frequencies up to 644.53 MHz
• Ultra-low jitter generation: 0.23 ps RMS (1.875–20 MHz) and 0.47 ps RMS (12 kHz–20 MHz)
• Programmable output signal formats: LVPECL, LVDS, CML, or CMOS
• Automatic and manual hitless switching with holdover capability during input loss

Applications

• Synchronous Ethernet line cards
• SONET OC-3/12/48 line cards
• PON OLT/ONU systems
• Carrier Ethernet switches and routers
• T1/E1/DS3/E3 line cards

Procurement Notes

Verify the specific speed grade suffix 'B' against the datasheet's ordering guide to confirm electrical characteristics, as the Si5315A variant exhibits different supply current and maximum output frequency limits. Ensure the package marking matches the 36-QFN outline dimensions. Confirm RoHS compliance status through official manufacturer documentation prior to integration.

Selection Notes

Select this component when designing for Synchronous Ethernet or Telecom applications requiring precise jitter attenuation without external VCXO components. The Si5315B speed grade supports a maximum output frequency of 125 MHz in CMOS format, whereas the Si5315A supports higher frequencies. Verify that the required loop bandwidth settings align with the ITU-T G.8262 standards for the target network synchronization application.

Part Context

The SI5315 belongs to Skyworks' family of jitter-attenuating clock multipliers designed for high-performance networking equipment. It replaces traditional PLL solutions requiring external loop filters and VCXOs by integrating these functions into a single highly integrated chip. This simplifies PCB layout and reduces component count for telecom and Ethernet infrastructure designs.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided source material.