SI5319A-C-GM

Overview

The Skyworks SI5319A-C-GM is a jitter-attenuating precision M/N clock multiplier utilizing third-generation DSPLL technology. It accepts an input frequency from 2 kHz to 710 MHz and generates an output from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) and supports selectable output formats including LVPECL, LVDS, CML, and CMOS. Powered by a single 1.8 V, 2.5 V, or 3.3 V supply, it integrates a loop filter with digitally programmable bandwidth ranging from 60 Hz to 8.4 kHz.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input of 2 kHz to 710 MHz
• Ultra-low jitter performance with generation as low as 0.3 ps rms (50 kHz–80 MHz)
• Integrated loop filter with selectable digital loop bandwidth from 60 Hz to 8.4 kHz
• Supports I2C or SPI programmability with on-chip voltage regulator for 1.8 V, 2.5 V, or 3.3 V operation

Applications

• 10G/40G/100G OTN line cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
• GbE/10GbE and 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Synchronous Ethernet applications

Procurement Notes

Verify the specific grade suffix 'A' against the official ordering guide to confirm frequency limits and electrical characteristics. Confirm package availability in the 36-lead QFN format. Ensure compatibility with required supply voltages (1.8 V, 2.5 V, or 3.3 V) and interface protocols (I2C or SPI). Check for RoHS compliance status in current documentation.

Selection Notes

Select this component for applications requiring sub-1 ps jitter performance and any-frequency synthesis. Use the DSPLLsim utility to determine optimal PLL divider settings and loop bandwidth configurations. Ensure the input clock source meets the specified swing and duty cycle requirements. Consider the thermal resistance characteristics if operating at maximum frequencies or temperatures.

Part Context

The SI5319 belongs to Skyworks' DSPLL family of jitter attenuators. It eliminates the need for external VCXO and loop filter components through high integration. The device provides loss-of-signal and loss-of-lock alarm outputs and supports VCO freeze capability for stable output during reference loss.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.