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The SI5319C-C-GM is a jitter-attenuating precision M/N clock multiplier utilizing Skyworks' third-generation DSPLL technology. It accepts an input frequency from 2 kHz to 710 MHz and generates an output from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) and includes an integrated loop filter with digitally selectable bandwidths ranging from 60 Hz to 8.4 kHz. It operates on a single supply voltage of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% and provides one configurable differential or single-ended output in LVPECL, LVDS, CML, or CMOS formats.
Verify the specific ordering suffix against the manufacturer's current documentation to ensure correct packaging and temperature grade. Confirm that the required output format and supply voltage align with the device's electrical specifications before procurement.
Select this component for applications requiring sub-1 ps jitter performance and flexible frequency synthesis. Ensure the design accommodates the 36-lead QFN package dimensions and utilizes the recommended PCB layout guidelines for optimal thermal and signal integrity.
The SI5319C-C-GM belongs to the Si5319 family of any-frequency precision clock multipliers. It is designed to replace discrete PLL solutions by integrating the loop filter and voltage regulator, thereby reducing board space and component count in high-performance timing applications.
Public confirmed substitute part numbers are not available in the provided source material.