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The Skyworks SI53204-A01AGMR is a 4-output PCIe clock fanout buffer supporting Gen 1 through Gen 6 specifications. It accepts differential or single-ended inputs from 10 MHz to 200 MHz and provides low-power, push-pull HCSL compatible differential outputs. The device operates on a single 1.5 V to 1.8 V supply with an output supply voltage of 1.05 V to 1.5 V (at 1.5 V input) or 1.05 V to 1.8 V (at 1.8 V input). Additive jitter is specified at a maximum of 0.02 ps RMS for Gen 6 compliance. It features adjustable slew rates, internal impedance matching, and individual hardware or I2C-controlled output enables.
Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and tape/reel configuration. Confirm RoHS-6 compliance status and Pb-free designation prior to procurement. Ensure the design supports the required 32-pin QFN thermal management requirements.
Select this component when a 4-channel PCIe clock distribution solution is required for Gen 1 through Gen 6 interfaces. Verify that the system power budget accommodates the dynamic supply current, which reaches approximately 31.5 mA at 1.8 V with all outputs active. Ensure the PCB layout supports the 32-pin QFN (5 x 5 mm) footprint and ground pad thermal connection.
This part belongs to the Si532xx family, which includes the Si53212 (12 outputs) and Si53208 (8 outputs). All members share identical electrical characteristics and pinout logic but differ in output count and package size. The Si53204 specifically utilizes a 32-pin QFN package designed for space-constrained industrial and consumer applications.
Public confirmed substitute part numbers are not available in the provided source material.