SI5324A-C-GM

Overview

The Si5324A-C-GM is a low-bandwidth, jitter-attenuating precision clock multiplier utilizing Skyworks' DSPLL technology. It accepts two input clocks from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device supports digitally programmable loop bandwidths between 4 Hz and 525 Hz. Key electrical parameters include an operating temperature range of -40°C to +85°C and supply voltages of 1.8V ±5%, 2.5V ±10%, or 3.3V ±10%. It features ultra-low jitter outputs as low as 290 fs rms (12 kHz–20 MHz) and integrates an on-chip voltage regulator.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from inputs up to 710 MHz
• Ultra-low jitter performance: 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz)
• Digitally programmable loop bandwidth from 4 Hz to 525 Hz for optimized jitter attenuation
• Supports hitless input clock switching with phase build-out and digital hold operation

Applications

• Broadcast video (3G/HD/SD-SDI, Genlock)
• Packet Optical Transport Systems (P-OTS), MSPP
• SONET OC-48/192/768, SDH/STM-16/64/256 line cards
• GbE/10/40/100G Synchronous Ethernet (LAN/WAN)

Procurement Notes

Verify the specific speed grade suffix 'A' against the manufacturer's ordering guide to confirm frequency limits and performance characteristics. Ensure the package type matches the 36-lead QFN specification. Confirm RoHS compliance and Pb-free status prior to procurement.

Selection Notes

Select this component when sub-1 ps jitter performance is required with loop bandwidths between 4 Hz and 525 Hz. It eliminates the need for external VCXO and filter components. Use the DSPLL sim utility to determine optimal PLL divider settings for minimizing phase noise and power consumption based on specific input/output frequency plans.

Part Context

The Si5324A-C-GM belongs to the Si5324 family of any-frequency precision clock multipliers. It is part of Skyworks Solutions' third-generation DSPLL technology lineup, designed for high-performance timing applications requiring significant jitter attenuation and flexible frequency synthesis capabilities.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.