SI5324C-C-GM

Overview

The SI5324C-C-GM is a low-bandwidth, jitter-attenuating precision clock multiplier utilizing Skyworks Solutions' 3rd-generation DSPLL technology. It accepts two input clocks from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device features digitally programmable loop bandwidths between 4 Hz and 525 Hz, achieving ultra-low jitter outputs as low as 290 fs rms (12 kHz–20 MHz). It supports configurable signal formats including LVPECL, LVDS, CML, and CMOS, operates on a single supply of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, and is housed in a 6 x 6 mm 36-lead QFN package.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input range of 2 kHz to 710 MHz
• Ultra-low jitter performance: 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz)
• Integrated loop filter with selectable digital loop bandwidth from 4 Hz to 525 Hz
• Supports hitless input clock switching with phase build-out and digital hold operation

Applications

• Broadcast video –3G/HD/SD-SDI and Genlock systems
• Packet Optical Transport Systems (P-OTS) and MSPP
• SONET OC-48/192/768 and SDH/STM-16/64/256 line cards
• GbE/10/40/100G Synchronous Ethernet (LAN/WAN)
• Data converter clocking and wireless base stations

Procurement Notes

Verify the specific speed grade suffix (e.g., -C-) against the ordering guide to ensure compliance with required maximum output frequencies. Confirm that the selected supply voltage aligns with the supported nominal levels of 1.8 V, 2.5 V, or 3.3 V. Ensure the application design accounts for the 36-lead QFN thermal characteristics and PCB land pattern requirements specified in the datasheet.

Selection Notes

Select the SI5324C-C-GM when sub-1 ps jitter performance is required with loop bandwidths between 4 Hz and 525 Hz. This model supports ITU-T G.8251 and Telcordia GR-253-CORE jitter specifications. Use the DSPLL sim utility to determine optimal PLL divider settings for minimizing phase noise and power consumption based on the specific input-to-output frequency translation ratio.

Part Context

The SI5324 series provides any-frequency synthesis and jitter attenuation without requiring external VCXO or filter components. The device includes configurable alarm outputs for Loss of Lock (LOL), Loss of Signal (LOS), and Frequency Offset (FOS). It supports I2C or SPI interfaces for programming input clock frequencies and multiplication ratios, enabling flexible integration into high-performance timing applications.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.