SI5324E-C-GMR

Overview

The SI5324E-C-GMR is a low-bandwidth, jitter-attenuating precision clock multiplier utilizing Skyworks' third-generation DSPLL technology. It accepts two input clocks from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device features ultra-low jitter outputs as low as 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz). It supports digitally programmable loop bandwidths between 4 Hz and 525 Hz, hitless input switching, and configurable signal formats including LVPECL, LVDS, CML, and CMOS. Powered by a single supply of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, it operates within an ambient temperature range of –40 °C to +85 °C in a 6 x 6 mm 36-lead QFN package.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from inputs up to 710 MHz
• Ultra-low jitter performance: 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz)
• Digitally programmable loop bandwidth from 4 Hz to 525 Hz for optimized jitter attenuation
• Hitless input clock switching with phase build-out and digital hold capability

Applications

• Broadcast video (3G/HD/SD-SDI, Genlock)
• Packet Optical Transport Systems (P-OTS), MSPP
• SONET OC-48/192/768, SDH/STM-16/64/256 line cards
• GbE/10/40/100G Synchronous Ethernet (LAN/WAN)

Procurement Notes

Verify the 'E' speed grade suffix against the official ordering guide, as it specifies distinct lock time and settle time parameters compared to standard variants. Confirm the 'R' suffix indicates tape-and-reel packaging. Ensure the component meets RoHS compliance and lead-free requirements specified in the datasheet.

Selection Notes

Select this variant when specific lock and settle time characteristics are required, as the 'E' grade differs from A/B/C/D grades. Ensure the application voltage matches the supported nominal levels (1.8 V, 2.5 V, or 3.3 V). Verify that the required output frequency falls within the 945 MHz general range or the 1.4 GHz select frequency range based on the divider settings.

Part Context

The SI5324E-C-GMR belongs to the Si5324 family of any-frequency precision clock multipliers. It shares the core DSPLL architecture and functional block diagram with other Si5324 variants but is distinguished by its specific electrical timing characteristics regarding lock and settle times. It is designed for high-performance timing applications requiring sub-1 ps jitter performance.

Replacement Considerations

Direct replacements include other Si5324 speed grades such as SI5324A-C-GMR, SI5324B-C-GMR, SI5324C-C-GMR, and SI5324D-C-GMR. Note that these variants have different lock and settle time specifications compared to the E grade.