SI5328B-C-GM

Overview

The SI5328B-C-GM is a jitter-attenuating precision clock multiplier designed for Synchronous Ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. It accepts two input clocks ranging from 8 kHz to 710 MHz and generates two output clocks ranging from 8 kHz to 808 MHz. The device operates from a single 2.5 V or 3.3 V supply, with typical current draw of 251 mA at 808 MHz LVPECL. It features digitally programmable PLL loop bandwidth (0.1 Hz to 6 Hz) and supports I2C or SPI interfaces.

Feature Summary

• Fully compliant with ITU-T G.8262, EEC options 1 and 2
• Ultra-low jitter generation as low as 0.3 ps rms (12 kHz–20 MHz)
• Dual clock inputs with manual or automatically controlled hitless switching
• Integrated loop filter with selectable loop bandwidth (0.1 Hz; 1 to 10 Hz)

Applications

• GbE/10GbE/100GbE Synchronous Ethernet
• Carrier Ethernet switches
• Carrier Ethernet routers

Procurement Notes

Verify the specific suffix 'GM' against the manufacturer's ordering guide to confirm package type and reel specifications. Confirm RoHS compliance status and lead times directly with Skyworks Solutions Inc. or authorized distributors prior to procurement.

Selection Notes

Select this component for designs requiring strict adherence to ITU-T G.8262 wander and jitter requirements. Ensure the design accommodates dual differential clock inputs and outputs. Utilize the DSPLLsim software utility to optimize PLL divider settings and loop bandwidth for minimal phase noise and power consumption.

Part Context

The SI5328 belongs to the Si5328 family of jitter-attenuating clock multipliers based on Skyworks' third-generation DSPLL technology. This technology integrates frequency synthesis and jitter attenuation into a highly integrated PLL solution, eliminating the need for external VCXO and loop filter components.

Replacement Considerations

Consult the official Skyworks Solutions replacement matrix for verified substitute part numbers. Do not assume functional equivalence with other models in the Si53xx family without verifying pinout and electrical parameter compatibility.

FAQ

What is the maximum output frequency of the SI5328?

The SI5328 can generate output clocks ranging from 8 kHz up to 808 MHz.

Does the SI5328 support hitless switching between input clocks?

Yes, the device supports hitless switching between its two synchronous input clocks in compliance with G.8262, minimizing phase transient propagation.

What control interfaces are available for programming the SI5328?

The device provides I2C or SPI interfaces for programmable input clock frequency and clock multiplication ratio configuration.