SI5328B-C-GMR

Overview

The SI5328B-C-GMR is a jitter-attenuating precision clock multiplier designed for Synchronous Ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. It accepts two input clocks ranging from 8 kHz to 710 MHz and generates two output clocks ranging from 8 kHz to 808 MHz. The device operates from a single 2.5 V or 3.3 V supply, with typical supply current of 251 mA at 808 MHz LVPECL output. It features digitally programmable PLL loop bandwidth (0.1 Hz to 6 Hz), integrated on-chip voltage regulator, and supports I2C or SPI interfaces.

Feature Summary

• Fully compliant with ITU-T G.8262, EEC options 1 and 2
• Ultra-low jitter generation as low as 0.3 ps rms (12 kHz–20 MHz)
• Dual clock inputs with manual or automatically controlled hitless switching
• Integrated loop filter with selectable loop bandwidth (0.1 Hz; 1 to 10 Hz)

Applications

• GbE/10GbE/100GbE Synchronous Ethernet
• Carrier Ethernet switches
• Carrier Ethernet routers

Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type, temperature range, and control interface configuration. Ensure compatibility with system power supply requirements (2.5 V or 3.3 V) and check for any recent product change notifications that may affect pinout or electrical specifications before finalizing procurement.

Selection Notes

Select this component when designing systems requiring strict adherence to ITU-T G.8262 wander and jitter specifications. The device eliminates the need for external VCXO and loop filter components due to its integrated DSPLL technology. Use the DSPLLsim software utility to determine optimal PLL divider settings and loop bandwidth configurations for minimizing phase noise and power consumption in your specific frequency translation scenario.

Part Context

The SI5328 belongs to Skyworks' third-generation DSPLL family, offering highly integrated frequency synthesis and jitter attenuation. It is specifically engineered for high-performance timing applications where traditional PLL solutions would require bulky external components. The device provides flexible input/output configurations and digital hold capability to maintain stable clock outputs during reference loss events.

Replacement Considerations

Consult the manufacturer's official cross-reference guide for verified substitute part numbers. Ensure any replacement maintains compatibility with ITU-T G.8262 compliance requirements and matches the required input/output frequency ranges and signal formats.