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The SI5328C-C-GMR is a jitter-attenuating precision clock multiplier designed for Synchronous Ethernet applications compliant with ITU-T G.8262/Y.1362. It accepts two differential input clocks from 8 kHz to 710 MHz and generates two independent output clocks up to 808 MHz using third-generation DSPLL technology. The device eliminates external VCXO and loop filter components, featuring digitally programmable PLL loop bandwidths (0.1 Hz to 10 Hz). It supports LVPECL, LVDS, CML, or CMOS output formats and includes hitless switching between inputs with sub-1 ps jitter generation.
Verify the specific suffix 'GMR' corresponds to the tape-and-reel packaging format required by your assembly line. Confirm that the 'C' grade designation meets your operational temperature range requirements of -40°C to +85°C before finalizing procurement specifications.
Select this component when strict adherence to ITU-T G.8262 wander and jitter masks is mandatory. Ensure the reference oscillator (TCXO/OCXO) selected provides sufficient stability, as the Si5328 relies on it for low-wander performance. Use the DSPLLsim utility to calculate optimal divider settings and loop bandwidth configurations for your specific frequency translation ratios.
This part belongs to the Si5328 family of precision clock multipliers. It is distinct from other Si53xx devices by its specific focus on Synchronous Ethernet compliance and its ability to handle dual differential inputs with hitless switching capabilities without external analog loop filters.
Direct replacements within the same package and pinout include other variants in the Si5328 series (e.g., Si5328A, Si5328B) if electrical parameters match. Cross-family replacements require careful verification of pin compatibility and software register mapping differences.