SI5335B-B05740-GM

Overview

The Skyworks SI5335B-B05740-GM is a web-customizable, any-frequency, any-output quad clock generator and buffer. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It features low phase jitter of 0.7 ps RMS, two selectable PLL loop bandwidths (1.6 MHz or 475 kHz), and up to five user-assignable pin functions. The component operates on a single core supply of 1.8, 2.5, or 3.3 V within an ambient temperature range of –40 to +85 °C.

Feature Summary

• MultiSynth fractional divider technology enables independent synthesis of four frequencies up to 350 MHz with 0 ppm error.
• Supports three independent, pin-selectable device configurations to replace multiple clock generators.
• Flexible output drivers support LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL formats with independent voltage selection.
• Low phase jitter of 0.7 ps RMS with selectable PLL loop bandwidths of 1.6 MHz or 475 kHz.

Applications

• PCI Express Gen 1/2/3/4 common clock generation
• Ethernet switch and router timing
• Processor and FPGA clocking
• DSL jitter attenuation

Procurement Notes

Verify the specific factory configuration encoded in the ordering suffix B05740 against system requirements, as this part is a custom-programmed device. Confirm that the required pin assignments for spread spectrum control, reset, and frequency select match the design constraints. Ensure the PCB land pattern accommodates the 24-QFN package dimensions.

Selection Notes

Select this model when four distinct, non-integer-related clock frequencies are required from a single device. Choose between the 1.6 MHz or 475 kHz loop bandwidth based on whether jitter attenuation for PCIe or DSL applications is necessary. Verify that the input reference source matches the supported formats, such as 25/27 MHz crystals or differential CMOS signals.

Part Context

This component belongs to the Si5335 family of highly flexible clock generators. It utilizes Skyworks' patented MultiSynth technology to provide precise frequency synthesis without integer boundary spurs. The device is designed to simplify system design by consolidating multiple clock sources into one programmable IC.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. As this is a factory-customized device, direct replacement requires matching the exact internal configuration file generated via the ClockBuilder Pro utility.

FAQ

What is the maximum output frequency supported by the Si5335?

The Si5335 supports output frequencies up to 350 MHz for LVPECL, LVDS, CML, SSTL, and HSTL formats. CMOS outputs are limited to 200 MHz, and HCSL outputs are limited to 250 MHz.

How does the device handle frequency synthesis error?

Using MultiSynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of the configuration.

Can the device operate in both clock generator and buffer modes?

Yes, the Si5335 can be configured as either a clock generator using the PLL or as a clock buffer device with the PLL bypassed.