SI5335D-B06097-GMR

Overview

The SI5335D-B06097-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer manufactured by Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth technology, ensuring 0 ppm frequency synthesis error. The device features four output banks supporting differential or single-ended configurations with independent voltage levels of 1.5, 1.8, 2.5, or 3.3 V. It operates on a single core supply (1.8, 2.5, or 3.3 V) and supports flexible inputs including external crystals (25/27 MHz), CMOS (up to 200 MHz), and differential/SSTL/HSTL (up to 350 MHz). Key electrical parameters include a typical phase jitter of 0.7 ps RMS, a core supply current of 45 mA in PLL mode, and an operating temperature range of –40 to +85 °C.

Feature Summary

• MultiSynth fractional divider technology enables independent synthesis of four frequencies with 0 ppm error.
• Supports three independent, pin-selectable device configurations for system flexibility.
• Configurable output drivers support LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL formats.
• Includes two selectable PLL loop bandwidths (1.6 MHz or 475 kHz) for jitter attenuation.

Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• DSL jitter attenuation and telecom line cards
• Processor and FPGA clocking

Procurement Notes

Verify the specific factory-customized configuration encoded in the ordering suffix B06097, as this part number represents a unique frequency plan and pin assignment generated via the ClockBuilder Pro utility. Confirm that the required input reference type and output driver voltages match the pre-programmed settings, as these cannot be altered post-manufacture without reordering.

Selection Notes

Select this component when a design requires four distinct, non-integer-related clock frequencies from a single package. Ensure the application utilizes inputs within the supported ranges: 25/27 MHz crystals, CMOS up to 200 MHz, or differential/SSTL/HSTL up to 350 MHz. Verify that the target output formats (e.g., LVDS, CMOS) are compatible with the specified maximum frequencies, such as 350 MHz for LVDS or 200 MHz for CMOS.

Part Context

The SI5335D variant belongs to the Si5335 family of quad clock generators. The 'D' suffix typically denotes specific performance characteristics or input/output capabilities compared to other family members like the Si5335A or Si5335C. This model is designed to replace multiple discrete clock oscillators and buffers, simplifying PCB layout and reducing component count in high-speed digital systems.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Due to the web-customized nature of the Si5335 series, exact functional replacements require identical frequency plans and pin assignments, which are unique to each ordering suffix.

FAQ

What is the maximum output frequency for CMOS format outputs?

The maximum output frequency for CMOS format outputs is 200 MHz.

Does the Si5335 support spread spectrum clocking?

Yes, the device supports PCIe-compliant spread spectrum control via user-assignable pins, with a default deviation of -0.5% and a modulation rate of 31.5 kHz.

How many independent device configurations can the Si5335 store?

The device supports up to three independent, user-assignable, pin-selectable device configurations.